Users of battery-powered devices such as notebook computers require that the devices be usable for long periods of time between battery recharges. This requirement has led to cascaded battery arrangements, in which a primary battery, a secondary battery, etc., are connected to the device in succession. Frequently an AC/DC converter is also provided to allow the user to conserve battery power when he is near a source of AC power. A connection for an external backup battery may also be provided.
Such an arrangement is illustrated in FIG. 1 wherein a primary battery B1 and a secondary battery B2 are connected via switches S1 and S2, respectively, to a load L, which could be a DC/DC converter supplying, for example, a notebook computer. The supply connections are made through a bus which is designated B.
Also connected to bus B is an AC/DC converter C3 which supplies power through a switch S3. The voltage supplied by primary battery B1 is designated V.sub.1, the voltage supplied by secondary battery B2 is designated V.sub.2, and the voltage supplied by AC/DC converter C3 is designated V.sub.3. The voltage at bus B is designated V.sub.bus. A backup battery B4 is also connected to bus B. Backup battery B4 provides power to some supervisory circuits and memory functions (not shown) when primary battery B1 and secondary battery B2 are discharged. To ensure that it is present when needed, backup battery B4 is not switched.
In the operation of this multiple battery arrangement, only one of switches S1, S2, and S3 would normally be closed at any given time. The remaining switches would be open. When power is supplied by primary battery B1, for example, switch S1 is closed and switches S2 and S3 are open.
As the power sources are switched in and out, the voltage across switches S1, S2, and S3 can vary both in magnitude and direction. This is illustrated in FIGS. 2A-2C. As shown in FIG. 2A, for example, the output V.sub.2 of battery B2 might be 14 V at a given point in time. If battery B2 is then supplying power, the voltage V.sub.bus would also equal 14 V. If battery B1 is fully charged, its output voltage V.sub.1 might be 18 V. In this case, the left side of switch S1 would be positively charged. On the other hand, assume the same situation except that battery B1 is discharged, so that V.sub.1 is 6 V. In this case, the right side of switch S1 is positively charged, as shown in FIG. 2B. A third alternative is illustrated in FIG. 2C where battery B1 is discharged, battery B2 is fully charged, and bus B is supplied by AC/DC converter C1. In the example, V.sub.1 is shown as equalling 6 V, V.sub.2 is shown as equalling 17 V, and V.sub.3 is shown as equalling 12 V. In this case, the right side of switch S1 is positively charged, and the left side of switch S2 is positively charged.
In summary, any of switches S1-S3 may have to withstand a voltage in either direction. The only thing known for certain is that all of the voltages applied to these switches will be above ground.
The device may also be equipped with an internal battery charger, as illustrated in FIG. 3. A battery charger C5 is connected to battery B1 via a switch S4 and to battery B2 via a switch S5. Battery charger C5 may be supplied from the output of AC/DC converter C3 or (optionally) directly from the power main. As illustrated in FIG. 4, battery charger C5 may deliver a voltage as high as 24 V for quick battery charging. In the condition illustrated in FIG. 4, battery B2 is being charged, and the V.sub.1 output of battery B1 is equal to 12 volts. Switch S4 therefore must withstand a voltage difference of 12 V. However, since deep discharging of a rechargeable battery is known to extend its life, V.sub.1 could drop to below 6 V, in which case switch S4 would need to withstand over 18 V, with its left side being positively charged. On the other hand, when battery charger C5 is not operative it may have a shorted or leaky characteristic, and switches S4 and S5 would then have to block voltages in the other direction. Therefore, switches S4 and S5 must also be bidirectional current blocking.
The foregoing would not represent a problem if switches S1-S5 were mechanical switches. However, it is preferable to use semiconductor technology, and in particular MOSFET technology, in fabricating these switches. Power MOSFETs are typically fabricated with a source-body short to ensure that the intrinsic bipolar transistor (represented by the source, body and drain regions) remains turned off at all times. The prior art teaches generally that a good source-body short is fundamental to reliable parasitic-bipolar-free power MOSFET operation. See, for example, "Power Integrated Circuits", by Paolo Antognetti, McGraw-Hill, 1986, pp. 3.27-3.34.
The use of a source-body short has the effect of creating a diode across the drain and body terminals of the MOSFET which is electrically in parallel with the MOSFET. For an N-channel device, the cathode of the diode is connected to the drain; for a P-channel device, the anode of the diode is connected to the drain. Thus, a MOSFET must never be exposed to voltages at its source-body and drain terminals which would cause the "antiparallel" diode to become forward-biased. FIGS. 5A-5D illustrate the polarity of the antiparallel diode (shown in hatched lines) for a vertical N-channel DMOS device (FIG. 5A), a vertical P-channel DMOS device (FIG. 5B), a lateral N-channel device (FIG. 5C), and a lateral N-channel DMOS device (FIG. 5D).
Accordingly, conventional MOSFETs are not suitable for switches S1-S5 because they are not capable of blocking bidirectional currents. In FIGS. 2A-2C, for example, the antiparallel diodes across switches S1 and S2 are shown in hatched lines, with their anode and cathode terminals arranged so as would be required to block the flow of current through the switches. If the polarity of the voltages across the switches were reversed, the antiparallel diodes would become forward-biased.
One possible solution to this problem would be to connect two MOSFETs in a back-to-back arrangement, as illustrated schematically in FIGS. 6A-6C. FIG. 6A illustrates a pair of NMOS devices having a common source, FIG. 6B illustrates a pair of NMOS devices having a common drain, and FIG. 6C illustrates a pair of PMOS devices having a common source. These back-to-back arrangements double the on-resistance of the switches, however, and therefore detract significantly from the amount of power delivered to the computer or other device.
Accordingly, what is needed is a bidirectional current blocking semiconductor switch which has the on-resistance of a normal MOSFET and yet does not contain an antiparallel diode across its drain and body terminals.